In a high-speed wireless communication system such as WLAN (wireless local area network) of IEEE 802.11a/g, a higher order modulation such as 16 QAM or 64 QAM is adopted for transmitting a large-volume signal efficiently within a limited frequency band. A chip for wireless applications that is used in this type of high-speed wireless communication system requires high power for signal processing. As a result, little progress has been seen in the application of the chips for wireless applications to terminals such as cellular phones with the exception of the comparatively slow IEEE 802.11b.
In recent years, the application of deep-submicron-CMOS devices to basebands with the aim of implementing signal processing with low power consumption has been advancing. As a result, the power-supply voltage of the baseband is lower.
In addition, there is a trend in chips for wireless applications to integrate a digital unit and RF unit to reduce costs. A chip in which a digital unit and RF unit are integrated is referred to as a “system-on-chip” (Soc).
In a System-on-chip, the RF unit must be produced by a micro-device and an RF circuit that operates at low voltage is therefore required. However, in conventional RF circuits that chiefly use the analog mode, element characteristics change when subjected to miniaturization and operation at low voltage is therefore problematic. In particular, a PLL is greatly affected by lower voltage in the RF circuit.
FIG. 1 is a block diagram showing an example of a PLL circuit of the analog type. In FIG. 1, the PLL circuit includes: phase comparator 1, charge pump 2, loop filter 3′, voltage-controlled oscillator (VCO) 4, and frequency divider 5.
Regarding the operation of this circuit, phase comparator 1 compares a reference signal (FREF signal) and the frequency-divided signal (CKV signal) of VCO4, and based on the comparison result, generates output signals S1 and S2. Output signal S1 shows the amount of advance of the phase of the FREF signal with respect to the CKV signal, and output signal S2 shows the amount of advance of phase of the CKV signal with respect to the FREF signal.
Output signals S1 and S2 are applied as input to charge pump 2. The output signal S3 of charge pump 2 is applied as input to loop filter 3′. Loop filter 3′ eliminates the high-frequency component of output signal S3 and applies output signal S3 from which this high-frequency component has been eliminated to VCO4 as control voltage S4.
When the frequency and phase of FREF signal and CKV signal match, this PLL circuit locks the frequency (fVCO) that VCO4 supplies and sets this fVCO to several times the frequency-division of the frequency of the FREF signal.
For example, when VCO4 is of the type that uses an inductor and the resonance frequency of a MOS varactor capacitance, fVCO changes according to the control voltage of the MOS varactor, which is a direct-current voltage. Increase to a high level in the modulation sensitivity, which is the amount of change of fVCO with respect to this change in the control voltage, gives rise to the problem in which that fVCO fluctuates due to the effect of power-supply noise or induction noise.
To solve this problem, a method has been proposed of setting the modulation sensitivity to a low level and using a plurality of resonance circuits. However, the range of the control voltage of a MOS varactor is limited to the linear region of the MOS varactor, and the problem therefore arises that lowering the power-supply voltage necessitates increasing the modulation sensitivity of the VCO, whereby the frequency of a local oscillator fluctuates due to noise outside and inside the chip.
As a means of solving this problem, a circuit for digitally controlling the VCO has been proposed (for example, refer to Document 1 (JP-A-2002-076886) and Document 2 (Journal of Solid-State Circuit, Vol. 39, No. 1/2, 2004, pp. 2278-2291).
In the related art, a time-control method is used in which a MOS varactor in a VCO is controlled not by the level of a direct-current voltage that is the control voltage, but by the ON/OFF time ratio realized by repeatedly turning the control voltage ON and OFF. When carried out with the control voltage turned ON/OFF at a fixed period, a large spurious signal is generated. As a result, a sigma-delta (ΣΔ) modulator is used in the art of the above-described documents to randomize the ON/OFF periods of the control voltage.
The operation of the PLL circuit used in the time-control method is described using FIG. 2.
The output signal of a digitally controlled VCO (dVCO) that oscillates at 2.4 GHz in numerically-controlled oscillator (NCO) 103 is converted to CKV signal 114 in sine-wave digital converter 106. Incrementor (INC) 118 generates phase θv(i) of the output signal of a digitally-controlled VCO by accumulating the number of clock transitions of the rising edge of CKV signal 114.
FREF signal 110, which is the output signal of a reference quartz oscillator, is retimed by CKV signal 114 and converted to CKR signal 112. Accumulator 102 generates the phase θr(k) of FREF signal 110 by accumulating frequency control (FCW) 116 that indicates a multiple of the target frequency for each rising edge of CKR signal 112.
Circuit 108 rounds off the decimal part of phase θr(k) of FREF signal 110. In addition, latch register 120 latches phase v(i) that was generated by incrementor 118 at the timing of CKR signal 112 to generate phase θr(k). Combining element 1/22 subtracts phase θv(k) generated at latch register ½ from phase θr(k) that was rounded off in circuit 108 to generate phase error signal θd(k).
Phase error signal θd(k), after being multiplied with a predetermined gain in gain element 105 in numerically-controlled oscillator 103, is applied as a signal for tuning to digitally controlled VCO (dVCO) 104.
A phase detection method that uses the accumulation of the number of clock transitions of the rising edge of this CKV signal is incapable of a realizing resolution that is equal to or less than the oscillation period of the VCO. As a result, in Documents 1 and 2, fractional phase detector 200 is further provided and time-digital converter (TDC) 201 in fractional phase detector 200 is used to detect micro-phase error.
As shown in FIGS. 3 and 4, in time-digital converter (TDC) 201, the position of a transition from “1” to “0” of CKV signal 114 is indicated by the delay time Δtr that is quantized from the edge that samples CKV signal 114 of FREF signal 110 of rising edge 302 of CKV signal 114. In addition, the position of the transition from “0” to “1” of CKV signal 114 is indicated by delay time Δtr that is quantized from the edge that samples CKV signal 114 of FREF signal 110 of falling edge 302 of CKV signal 114. In addition, delay times Δtr and Δtr are represented using a multiple of the time resolution Δtres.
Here, small phase error φF is given by−Δtr/2(Δtf−Δtr) when Δtf>Δtr, and is given by 1−Δtr/2(Δtr−Δtf) when Δtr>Δtf.
FIG. 5 is a circuit diagram that shows an example of time-digital converter 201 for detecting the phase error equal to or less than the period of CKV signal shown in FIG. 2. In FIG. 5, time-digital converter 500 is made up from: a plurality of delay elements 502, a plurality of latch/registers 504. Delay elements 502 are made up from inverters.
CKV signal 114 that is generated at dVCO is successively delayed at the plurality of delay elements 502. Each of delayed CKV signals 114 are latched by respective latch/register 504 at the rising edge of FREF signal 110. The total of the delay time realized by the plurality of delay elements 502 can adequately cover the clock periods of CKV signals 114, and the phase error can be detected by resolution Δtres that is determined by the delay time of the delay elements.
FIG. 6 shows timing chart 600 for explaining the operation of the circuit shown in FIG. 5. Each of the plurality of latch/registers 504 latches a respective delayed CKV signal 114 at the timing of the rising edge of FREF signal 110. In this way, instantaneous value 604 that indicates the size of the delay of CKV signal is obtained from rising edge 602 of FREF signal 110. This instantaneous value 604 can be considered a value that indicates the phase difference of FREF signal 110 and CKV signal by a digital value.
A PLL circuit precisely controls the frequency of dVCO 104 by using a digital value to control a ΣΔ-modulator.
This digital control of a VCO enables the generation of a stable and precise oscillation signal even in low-voltage operation of a deep-submicron-CMOS device.